How does the circuit board factory solve the EMI problem in multi-layer PCB design

1. Power bus

Properly placing a capacitor of appropriate capacity near the power supply pin of the IC can make the jump of the IC output voltage come faster. However, the problem doesn't stop there. Due to the finite frequency response nature of capacitors, this prevents them from generating the harmonic power required to cleanly drive the IC's output over the full frequency band. In addition, the transient voltages developed on the power bus bars will cause a voltage drop across the inductor in the decoupling path. These transient voltages are the main source of common-mode EMI interference. How should we solve these problems?

As far as the IC on the board of our circuit board factory is concerned, the power plane around the IC can be regarded as an excellent high-frequency capacitor, which can collect the part of the energy leaked by the discrete capacitor that provides high-frequency energy for a clean output. In addition, the inductance of an excellent power plane should be small, so that the transient signal synthesized by the inductance is also small, thereby reducing common-mode EMI.

Of course, the connection from the power supply layer to the IC power supply pin must be as short as possible, because the rising edge of the digital signal is getting faster and faster, it is best to connect directly to the pad where the IC power supply pin is located, which will be discussed separately.

To control common-mode EMI, a power plane that facilitates decoupling and has sufficiently low inductance must be a pair of reasonably well-designed power planes. One might ask, how good is good? The answer to this question depends on the layering of the power supply, the materials between the layers, and the operating frequency (ie, a function of the IC's rise time). Usually, the pitch of the power layer is 6mil, and the interlayer is FR4 material, so the equivalent capacitance per square inch of the power layer is about 75pF. Obviously, the smaller the layer spacing, the larger the capacitance.

There are not many devices with a rise time of 100 to 300 ps, but according to the current IC development speed, devices with a rise time in the range of 100 to 300 ps will occupy a high proportion. For circuits with 100 to 300ps rise time, 3mil layer spacing will no longer be suitable for most applications. At that time, it is necessary to adopt layering technology with a layer spacing of less than 1mil and replace the FR4 dielectric material with a material with a very high dielectric constant. Today, ceramic and ceramic plastics can meet the design requirements of 100 to 300 ps rise time circuit.

Although new materials and approaches may be employed in the future, for today's common 1 to 3 ns rise time circuits, 3 to 6 mil layer spacing and FR4 dielectric material, it is usually enough to handle high-end harmonics and keep the transient signal low enough, that is , common mode EMI can be reduced very low. The PCB layered stack-up design example given in this article will assume a layer spacing of 3 to 6 mils.

2. Electromagnetic shielding

From the perspective of signal routing, a good layering strategy should be to put all signal routing on one or several layers, and these layers are next to the power layer or ground layer. For the power supply, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer is as small as possible. This is what we call the "layering" strategy.

3. PCB stacking

What kind of stacking strategy helps to shield and suppress EMI? The following layered stacking scheme assumes that the power supply current flows on a single layer, and single or multiple voltages are distributed in different parts of the same layer. The case of multiple power planes is discussed later.

4.4 layer board

There are several potential problems with the 4-layer board design. First of all, for a traditional four-layer board with a thickness of 62mil, even if the signal layer is on the outer layer and the power and ground layers are on the inner layer, the distance between the power layer and the ground layer is still too large.

If the cost requirement is the first, you can consider the following two alternatives to the traditional 4-layer board. Both of these solutions improve EMI suppression performance, but only when the component density on the board is low enough and there is enough area around the components to place the required power supply copper plane.

The first is the preferred solution. The outer layers of the PCB are ground layers, and the middle two layers are signal/power layers. The power supply on the signal layer is routed with wide traces, which makes the path impedance of the power supply current low, and the impedance of the signal microstrip path is also low. From an EMI control point of view, this is the best 4-layer PCB structure available. In the second scheme, the outer layer uses power and ground, and the middle two layers use signals. Compared with the traditional 4-layer board, the improvement of this solution is smaller, and the interlayer impedance is as poor as the traditional 4-layer board.

If you want to control the trace impedance, the above stacking schemes must be very careful to arrange the traces under the power and ground copper islands. In addition, copper islands on power or ground planes should be interconnected as much as possible to ensure DC and low frequency connectivity.

5.6 layer board

If the component density on the 4-layer board is relatively high, it is best to use a 6-layer board. However, some stacking schemes in the 6-layer board design do not have a good shielding effect on the electromagnetic field, and have little effect on reducing the transient signal of the power bus. Two examples are discussed below.

In the first example, the power supply and the ground are placed on the second and fifth layers respectively. Due to the high impedance of the power supply copper, it is very unfavorable to control the common mode EMI radiation. However, from the point of view of impedance control of the signal, this approach is very correct.

In the second example, the power supply and ground are placed on the third and fourth layers respectively. This design solves the problem of power supply copper impedance. Due to the poor electromagnetic shielding performance of the first and sixth layers, differential mode EMI increases.

This design can solve differential-mode EMI problems if the number of signal lines on the two outer layers is minimal and the trace lengths are short (less than 1/20 of the signal's highest harmonic wavelength). The suppression of differential mode EMI is particularly good by filling the non-component and non-trace area on the outer layer with copper and grounding the copper area (every 1/20 wavelength interval). As mentioned earlier, it is necessary to connect the copper pour area to the internal ground plane at multiple points.

The general-purpose high-performance 6-layer board design generally arranges the 1st and 6th layers as ground layers, and the 3rd and 4th layers take power and ground. Since there are two centered double microstrip signal line layers between the power plane and the ground plane, the EMI suppression capability is excellent. The disadvantage of this design is that there are only two routing layers. As mentioned earlier, if the outer layer traces are short and copper is laid in the trace-free area, the same stacking can also be achieved with a traditional 6-layer board.

Another 6-layer board layout is signal, ground, signal, power, ground, signal, which enables the environment required for advanced signal integrity designs. The signal plane is adjacent to the ground plane, and the power plane and the ground plane are paired. Apparently the downside is the unbalanced stacking of layers.

This often creates troubles for manufacturing. The solution to the problem is to fill all the blank areas of the third layer with copper. After filling the copper, if the copper density of the third layer is close to the power layer or ground layer, this board can be regarded as a structurally balanced circuit board. . The copper filling area must be connected to power or ground. The distance between connecting vias is still 1/20 wavelength, not necessarily connecting everywhere, but ideally should be connected.

6.12 layer board

Since the insulation isolation layer between the multilayer boards is very thin, the impedance between the layers of the 10 or 12-layer circuit board is very low. As long as there is no problem with the layering and stacking, excellent signal integrity can be expected. It is more difficult to process and manufacture 12-layer boards with a thickness of 62mil, and there are not many manufacturers that can process 12-layer boards.

Since there is always an insulating layer between the signal layer and the circuit layer, it is not optimal to allocate the middle 6 layers to route the signal lines in the 10-layer board design. Also, it is important to have the signal layer adjacent to the loop layer, i.e. the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, signal.

This design provides a good path for the signal current and its return current. The proper routing strategy is to route the first layer along the X direction, the third layer along the Y direction, the fourth layer along the X direction, and so on. Intuitively looking at the wiring, layer 1 and layer 3 are a pair of layered combinations, layers 4 and 7 are a pair of layered combinations, and layers 8 and 10 are the last pair of layered combinations. When it is necessary to change the routing direction, the signal lines on the first layer should go to the third layer through "via holes" and then change the direction. In practice, it may not always be possible to do so, but as a design concept try to stick to it.

Similarly, when the routing direction of the signal changes, it should go from the 8th layer to the 10th layer or from the 4th layer to the 7th layer through the via hole. Routing this way ensures the tightest possible coupling between the forward path and the return path of the signal. For example, if the signal is routed on the first layer, and the loop is routed on the second layer and only on the second layer, then the signal on the first layer is transferred to the third layer through "vias", and its The loop is still on layer 2, thus maintaining the characteristics of low inductance, large capacitance and good electromagnetic shielding performance.

What if the actual wiring is not like this? For example, the signal line on the first layer goes to the 10th layer through a via hole. At this time, the loop signal has to find the ground plane from the 9th layer, and the loop current needs to find the nearest ground via (such as Ground pin for components such as resistors or capacitors). Really lucky if there happens to be such a via nearby. If there are no such close vias available, the inductance will increase, the capacitance will decrease, and EMI will definitely increase.

When the signal line must leave the current pair of wiring layers to other wiring layers through the via hole, the ground via hole should be placed next to the via hole, so that the loop signal can smoothly return to the appropriate ground layer. For the layered combination of layer 4 and layer 7, the signal loop will return from the power layer or ground layer (ie, layer 5 or layer 6), because the capacitive coupling between the power layer and the ground layer is good, and the signal is easy to transmit.

7. Design of multiple power layers

If the two power planes of the same voltage source need to output a large current, the circuit board should be laid out as two sets of power planes and ground planes. In this case, insulating layers are placed between each pair of power and ground planes. In this way, we get the two pairs of power bus bars with equal impedance that we expect to divide the current equally. If the stacking of power planes creates unequal impedances, the shunt will not be uniform, the transient voltage will be much larger, and EMI will increase dramatically.

If there are multiple power supply voltages with different values on the board, multiple power planes will be required accordingly, keeping in mind to create separate pairs of power and ground planes for the different power supplies. In both cases, keep in mind the manufacturer's requirement for a balanced structure when determining the location of the mating power and ground planes on the board.

8. Summary

Given that most engineers design boards that are traditional 62mil thick PCBs with no blind or buried vias, the discussion of board layering and stackup in this article is limited to that. For circuit boards with too much difference in thickness, the layering scheme recommended in this article may not be ideal. In addition, the processing process of circuit boards with blind or buried vias is different, and the layering method in this paper is not applicable.

In circuit board design, the thickness, via process and the number of layers of the circuit board are not the key to solving the problem. Excellent layered stacking is to ensure the bypass and decoupling of the power bus bar, and minimize the transient voltage on the power layer or ground layer And the key to shielding the electromagnetic field of the signal and power supply. Ideally, there should be an insulating isolation layer between the signal trace layer and its return ground layer, and the paired layer spacing (or more than one pair) should be as small as possible. According to these basic concepts and principles, a circuit board that can always meet the design requirements can be designed. Now that the rise times of ICs are already short and will be even shorter, the techniques discussed in this article are essential to solving EMI shielding problems.

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